1. Field of the Invention
The present invention relates to a driving apparatus and method for an active matrix type liquid crystal display (LCD) apparatus having row and column electrodes in a lattice arrangement, picture element electrodes for display located in regions defined by the row and column electrodes in a matrix arrangement, and switching transistors connected to the picture element electrodes and the row and column electrodes.
2. Description of the Prior Art
FIG. 3 shows an exemplary active matrix type LCD apparatus of 4.times.4 matrix. Row electrodes (gate electrode wirings) 1-4 and column electrodes (source electrode wirings) 5 are arranged in a lattice in the row and column directions. In regions defined by the row and column electrodes, picture element electrodes 20 are arranged in a matrix. At each of the crossings of the row and column electrodes, a switching transistor 10 is provided. For the switching transistor 10, for example, a thin film transistor (TFT) is used. Gate terminals 11 of the switching transistors 10 are respectively connected to the row electrodes 1-4. Source terminals 12 of the switching transistors 10 are connected to the column electrodes 5, and drain terminals 13 thereof are connected to the corresponding picture element electrodes 20.
The column electrodes 5 are connected to a column electrode driving circuit 40. The column electrode driving circuit 40 periodically and sequentially applies data for one line to the column electrodes 5. When the switching transistors 10 are turned ON by a pulse applied from a row electrode driving circuit 30 to the row electrodes 1-4, a signal VS applied to each of the column electrodes 5 is applied to each of the picture element electrodes 20. By sequentially scanning a pulse applied from the row electrode driving circuit 30 to the row electrodes 1-4, and by varying column electrode data in synchronism with the timing, and image is displayed on the active matrix type LCD apparatus.
FIG. 4 schematically shows a configuration of the row electrode driving circuit 30. The row electrode driving circuit 30 includes a shift register 31, and four AND gates 32 respectively connected to output terminals Q1, Q2, Q3, and Q4 of the shift register 31. The shift register 31 inputs data SP at a data terminal (a terminal D) and a clock pulse CL at a clock terminal (a terminal CK), and shifts the data SP in accordance with the clock pulse CL. As a result, the shift register 31 outputs the shifted data SP to the AND gates 32 at the respective output terminals Q1, Q2, Q3, and Q4. The clock pulse CL and a LOW signal are also input into the AND gates 32. The AND gates 32 AND these input signals, and output gate-on pulses VG1-VG4 onto the row electrodes 1-4, respectively.
FIG. 5 shows waveforms of signals. Hereinafter, a waveform indicated by (N) in a figure is referred to as an Nth waveform. For example, in FIG. 5, the first to fourth waveforms shows those of the gate-on pulses VG1-VG4, the fifth waveform shows that of the clock pulse CL, the sixth waveform shows that of the data SP, and the seventh waveform shows that of the LOW signal.
Conventionally, each of the gate-on pulses VG1-VG4 applied to the row electrodes 1-4 is a one-shot pulse, as shown by the first to fourth waveforms in FIG. 5. The gate-on pulses have a waveform including an HI (high level) period and a LOW (low level) period. During the HI period, the corresponding switching transistor 10 is in an ON state, and during the LOW period, the corresponding switching transistor 10 is in an OFF state. As a result, only during the HI period of each of the gate-on pulses VG1-VG4, the signal VS shown by the eighth waveform in FIG. 5 is applied to the picture element electrodes 20 connected to the respective row electrodes 1-4 through the corresponding switching transistors 10. Accordingly, electrical charges are charged in a liquid crystal layer as a display medium of picture elements. The electrical charges are held in the liquid crystal layer during the LOW period of the gate-on pulses VG1-VG4, and each of the picture elements exhibits a transmissivity depending on the voltage applied to the picture element.
According to the conventional driving method shown in FIG. 5, in order to prevent the liquid crystals from deteriorating due to a DC voltage applied to an LCD apparatus, the polarity of the applied voltage is inverted for every line (for each of the row electrodes 1-4). In other words, a 1H inversion (the polarity is inverted every one horizontal period) system is adopted. The 1H period (one horizontal period) coincides with a period of a National Television System Committee (NTSC) television signal (1H=63.5 .mu.s).
When the gate-on pulse VG1 of the first waveform in FIG. 5 is applied to the row electrode 1 in FIG. 3, and the signal VS of the eighth waveform in FIG. 5 is applied to the column electrode 5 in FIG. 3, according to the driving method mentioned above, the potential of a picture element electrode 20 at the crossing of the row and column electrodes 1 and 5 varies. If the gate-on period is sufficiently long, the liquid crystal layer is sufficiently charged. The potential variation VLC of the picture element 20 at the crossing is saturated, as shown by the ninth waveform in FIG. 5.
In order to increase the scanning speed for improving the functionality of the LCD apparatus, it is necessary to shorten the gate-on period. However, if the gate-on period is shortened, the liquid crystal layer is insufficiently charged. This results in an insufficient voltage application to the liquid crystal layer, and causes problems in displaying an image as follows.
For example, we consider the case of the transmission type LCD apparatus of a normally white system (during no voltage application: white (light is transmitted), during voltage application: black (light is shielded)). As the scanning speed is increased, the gate-on time period is not sufficient. This causes a short of charge phenomenon in which sufficient voltage is not applied to the liquid crystal layer. As a result, there arises problems in that the resulting display is whitish and a sufficient display contrast cannot be obtained, as compared with the case where the charging is sufficiently performed by applying a voltage of the same level to a column electrode.
The above-mentioned problems are specifically shown by a ninth waveform in FIG. 6. FIG. 6 shows signal waveforms in a driving method, one horizontal scanning period is set to be one-half of the period of the NTSC television signal. The gate-on pulses VG1-VG4 respectively shown by first to fourth waveforms in FIG. 6 are applied to the row electrodes 1-4. The gate-on pulses VG1-VG4 are produced by inputting a clock pulse CL of a fifth waveform, data SP of a sixth waveform, and a LOW signal of a seventh waveform in FIG. 6 into the respective input terminals of the row electrode driving circuit 30. The signal VS shown by an eighth waveform in FIG. 6 indicates a signal to be applied to the column electrodes 5 shown in FIG. 3.
A ninth waveform VLC in FIG. 6 represents the variation in potential applied to a picture element electrode 20 at the crossing of the row electrode 1 and the column electrode 5, when the signal VS shown by the eighth waveform in FIG. 6 is applied to the column electrode 5. Since the gate-on period of the gate-on pulse of the first waveform is shorter than that of the first waveform shown in FIG. 5, the charge to the liquid crystal layer is not sufficient. As a result, the potential of VLC cannot reach a sufficient level.
The potential of VLC should reach the level indicated by a broken line of the ninth waveform in FIG. 6. However, in actuality the potential of VLC only reaches the level indicated by the solid line thereof.
For the reasons mentioned above, there arises a problem that display contrast sufficient for the display quality of the LCD apparatus cannot be obtained according to the driving method shown in FIG. 6.